Silvaco
Silvaco, inc. is a privately owned provider of electronic design automation (EDA) software[1] and TCAD process and device simulation software.[2] Silvaco was founded in 1984 by Dr. Ivan Pesic. It is headquartered in Santa Clara, California with 11 offices worldwide, and in 2006 the company had about 250 employees worldwide.
Silvaco provides analog semiconductor process, device and design automation solutions in CMOS, bipolar, SiGe and compound technologies. Customers include leading fabless semiconductor companies, integrated semiconductor manufacturers, foundries, and universities worldwide.
History
Founded by Dr Ivan Pesic in 1984, the company acquired EDA Pioneer Simucad in 2003.[3] Silvaco delivers EDA and Stanford-based TCAD products with support and engineering services to provide semiconductor process and device simulation solutions. Worldwide customers include leading foundries, fabless semiconductor companies, integrated semiconductor manufacturers, universities, and semiconductor designers.
The company is privately held, internally funded, debt-free, and owns all of its office buildings. It is headquartered in Santa Clara, California, with eight offices worldwide including US offices in Austin, Texas, North Chelmsford, Massachusetts, and Phoenix, Arizona.
Litigation
Silvaco has been involved in litigation against such companies as Circuit Semantics, Inc. (CSI),[4] Technology Modeling Associates, MetaSoftware and Avanti Corporation for theft of trade secrets. Silvaco won a $20 million judgment from Avanti just prior to the latter company's acquisition by Synopsys.[5] In 2008, legal action by Silvaco against Cypress Semiconductor, Inc. led the California Court of Appeal to make a ruling clarifying when the statute of limitations for theft of trade secrets begins. The ruling stated that "statute of limitations on a cause of action for misappropriation begins to run when the plaintiff has any reason to suspect that the third party knows or reasonably should know that the information is a trade secret."[6][7][8]
Products
TCAD products
- ATHENA is a group of process simulation products that enables process and integration engineers to develop and optimize semiconductor manufacturing processes. ATHENA provides a platform for simulating ion implantation, diffusion, etching, deposition, lithography, oxidation, and silicidation of semiconductor materials. It replaces costly wafer experiments with simulations.[9]
- ATLAS is a group of device simulation products enables device technology engineers to simulate the electrical, optical, and thermal behavior of semiconductor devices. It provides a physics-based, modular, and extensible platform to analyze DC, AC, and time domain responses for all semiconductor based technologies in 2 and 3 dimensions.
- MERCURY is a MESFET and HEMT group of device simulation products which contains: FastBlaze, FastNoise, FastDevEdit and Mocasim. FastBlaze device simulator uses physics based calculations to generate highly accurate electrical characteristics of MESFET and HEMT devices. Mocasim calculates fundamental electron transport properties of Zincblende and Wurtzite semiconductors. MERCURY framework combines the speed of FastBlaze with the Monte Carlo flexibility of Mocasim to perform statistical design of MESFET and HEMT devices.
- Virtual Wafer Fab or "VWF" is a group of TCAD products that automate and emulate physical wafer manufacturing. These tools facilitate the input, execution, run-time optimization, and results processing of TCAD simulations into a flow managed through a common database. It can be used for such tasks as designing more efficient solar cells for use in space.[10]
EDA products
The company supplies integrated EDA software in the areas of Analog/Mixed-Signal/RF, Custom IC CAD, Interconnect Modeling, and Digital CAD.
- Analog/Mixed-Signal/RF products
- UTMOST III SPICE modeling software generates SPICE models for analog, digital, mixed-signal, and RF applications.
- UTMOST IV optimization module provides a database-driven environment for the generation of SPICE models and macro-models for analog, mixed-signal and RF applications.
- SPAYN, meaning Statistical Parameter and Yield Analysis, is a statistical modeling tool for analyzing variances from model parameter extraction sequences, electrical test routines, and circuit test measurements.
- Gateway is a schematic editor. It is a front end for Silvaco's Analog/Mixed Signal/RF IC Design Platform, and is integrated with the company's circuit simulation, layout, DRC/LVS/LPE, and parasitic extraction tools.
- SmartSpice is an analog circuit simulator used in the design of analog circuits and analog mixed-signal circuits. It can analyze critical nets and characterize cell libraries.
- SmartSpiceRF is a harmonic balance based RF simulator. It provides a set of steady-state large-signal analyses and measurements to design GHz range RF ICs driven with multi-tone sources.
- Harmony is an analog and mixed-signal circuit simulator. It simulates circuitry expressed in Verilog, SPICE, Verilog-A and Verilog-AMS, and dynamically links in the capabilities of the SmartSpice Circuit Simulator and SILOS Verilog Simulator at run time.
- Verilog-A is a language for SmartSpice. Compiled or interpreted Verilog-A language combined with SmartSpice provides designers with an environment for the design and verification of analog and mixed-signal circuits.
- Custom IC CAD
- EXPERT is a layout editor. It offers layout viewing, editing features, and scripting for automation with parameterized cells (PCells).
- Guardian is a suite of DRC/LVS/LPE physical verification products. They provide verification of analog, mixed signal and RF IC designs, perform design rule checks (DRC), layout vs. schematic (LVS) comparisons, and layout parameter extractions (LPE).
- HIPEX is a set of full-chip parasitic extraction products. They perform extraction of parasitic capacitors and resistors from hierarchical layouts into hierarchical transistor-level netlists using nanometer process technology.
- Interconnect Modeling
- QUEST is a high frequency parasitic extractor. It calculates 3D frequency-dependent inductance, resistance, capacitance and capacitive loss for any multi-port network for RF SPICE analysis.
- CLEVER is a physics-based parasitic extractor. It uses 3D field solvers to convert the mask data of a cell and relevant process information into a SPICE netlist. This process removes inaccuracies resulting from traditional, rule-based parasitic extractors.
- STELLAR is a core parasitic extractor. It fills the circuit size gap between typical small cell solvers and full chip extractors.
- Digital CAD
- SILOS is an IEEE-1364-2001 compliant Verilog simulator. It offers debugging features in a design environment for FPGA, PLD, ASIC, and custom digital designs.
- HyperFault is an IEEE-1364-2001 compliant mixed-level fault simulator that analyses test vectors’ ability to detect faults.
- AccuCell is a characterization and modeling tool that characterizes and validates standard cell libraries, I/Os, and custom cells.
- AccuCore provides transistor and gate level full-chip STA with automatic block characterization.
Process Design Kits (PDKs)
Silvaco offers process design kits (PDKs) for analog, mixed-signal and RF design teams. These are collections of verified data files that are used by a set of custom IC design EDA tools to provide a design flow. Such data files include schematic symbols, parameterized cells (PCells), DRC/LVS runsets, parasitic extraction runsets, and scripts to automate the generation and verification of design data.
Foundry process-specific models, symbols, and rule decks are integrated and tested with Silvaco custom IC design tools and PCells to create an AMS/RF design environment.
References